FIG. 39 shows the arrangement of a conventional voltage generator disclosed in Japanese Patent Laid-Open No. 2004-187188. The voltage generator includes resistors 3020 to 3024 that are connected in series. Voltage input terminals 3002 and 3003 are connected to the ends of the resistors 3020 to 3024. When external reference voltages VRT and VRB are supplied to the voltage input terminals 3002 and 3003, respectively, the resistors 3020 to 3024 divide the voltages to generate a plurality of different reference voltages.
The arrangement shown in FIG. 39 constructs an analog/digital converter as a whole. An analog signal is input from an input terminal 3001 to comparators (voltage comparators) 3031 to 3034. The reference voltages output from the voltage generator are supplied to the comparators 3031 to 3034. The comparators 3031 to 3034 hold the result of comparison between the reference voltage and the analog signal for each clock input. Boundary detectors 3041 to 3044 detect the boundaries between the determination results of the comparators 3031 to 3034. First and second encoders 3050 and 3070 convert the outputs from the boundary detectors 3041 to 3044 into binary data. Flip-flops 3061 to 3064 temporarily hold data output from the encoder 3050. Flip-flops 3081 to 3084 temporarily hold data output from the encoder 3070. Referring to FIG. 39, reference numerals 3004 to 3007 denote clock input terminals; 3008 to 3011, data output terminals; and 3090 to 3094, transmission lines.
Although FIG. 39 illustrates an example in which the voltage generator is applied to an analog/digital converter, the voltage generator may be mounted in the control circuit of a vector sum phase shifter. FIG. 40 is a block diagram showing the arrangement of a vector sum phase shifter. FIGS. 41A to 41D are constellation diagrams of signals of the respective portions of the vector sum phase shifter shown in FIG. 40 plotted on a plane.
The vector sum phase shifter includes a 90° phase shifter 1000, two sign inverters 1001I and 1001Q, two variable gain amplifiers 1002I and 1002Q, combiner 1003, and control circuit 1004. This vector sum phase shifter is disclosed in reference, Kwang-Jin Koh, et al., “0.13-μm CMOS Phase Shifters for X-, Ku-, and K-Band Phased Arrays”, IEEE Journal of Solid-State Circuits, vol. 42, no. 11, November 2007, pp. 2535-2546”.
The operation of the vector sum phase shifter shown in FIG. 40 will be described below assuming that an input signal VIN is an ideal sine wave. FIG. 41A shows the input signal VIN. The 90° phase shifter 1000 receives the input signal VIN, and outputs an in-phase signal VINI and a quadrature signal VINQ which are 90° degrees out of phase. On the constellation diagram with an in-phase component (I) plotted along the abscissa and a quadrature component (Q) plotted along the ordinate, the in-phase signal VINI can be represented by only the in-phase component (I), and the quadrature signal VINQ can be represented by only the quadrature component (Q), as shown in FIG. 41B. If the two signals VINI and VINQ are combined, a signal corresponding to a point 220 (at an angle of 45° and an amplitude of 21/2) in FIG. 41B can be obtained.
The in-phase signal VINI and the quadrature signal VINQ are input to the pair of sign inverters 1001I and 1001Q, respectively. The sign inverters 1001I and 1001Q switch, based on the levels of control signals SI and SQ, respectively, between directly outputting the input signal and outputting the signal after inverting the voltage sign. On the constellation diagram, the in-phase signal VINI is output as one of the signal corresponding to the in-phase component (I) and a signal obtained by rotating the in-phase component (I) by 180°, and the quadrature signal VINQ is output as one of the signal corresponding to the quadrature component (Q) and a signal obtained by rotating the quadrature component (Q) by 180°, as shown in FIG. 41C. If the two signals VINI and VINQ are combined, a signal corresponding to one of points 221, 222, 223, and 224 (at an angle of 45°, 135°, 225°, or 315° and an amplitude of 21/2) in FIG. 41C can be obtained.
To obtain finer phase shift angles, the output signals from the pair of sign inverters 1001I and 1001Q are input to the pair of variable gain amplifiers 1002I and 1002Q, respectively. The variable gain amplifiers 1002I and 1002Q change the gains based on the levels of control signals DAT and DAQ, respectively, and consequently change the amplitudes of the input signals and output them. The combiner 1003 vector-combines an in-phase signal VXI and a quadrature signal VXQ output from the pair of variable gain amplifiers 1002I and 1002Q, and outputs the combined signal to the outside as a phase shifter output VOUT.
For example, when the gain on the in-phase signal side is set to 1, and that on the quadrature signal side is set to 0, a signal corresponding to a point 225 (at an angle of 0° and an amplitude of 1) in the constellation diagram of FIG. 41D can be obtained as the phase shifter output VOUT. Similarly, when the gain on the in-phase signal side is set to cos(22.5°)≈0.92, and that on the quadrature signal side is set to sin(22.5°)≈0.38, a signal corresponding to a point 226 (at an angle of 22.5° and an amplitude of (0.922+0.382)1/2=1) in FIG. 41D can be obtained as the phase shifter output VOUT. When the gain on the in-phase signal side is set to cos(45°)≈0.71, and that on the quadrature signal side is set to sin(45°)≈0.71, a signal corresponding to a point 227 (at an angle of 45° and an amplitude of (0.712+0.712)1/2=1) in FIG. 41D can be obtained as the phase shifter output VOUT.
The above-described three setting examples are operation examples in the first quadrant (0° to 90°). Controlling the pair of sign inverters 1001I and 1001Q allows to obtain a signal having an arbitrary phase and an amplitude of 1 (constant independently of the phase) throughout the four quadrants (0° to 360°). That is, when the gain on the in-phase signal side is set to cos(φ) and the gain on the quadrature signal side is set to sin(φ) a signal having an angle φ and an amplitude of 1 can be obtained as the phase shifter output VOUT.
For the operation of the above-described vector sum phase shifter, the control circuit 1004 receives a digital signal DGTL containing the information of the phase φ to be output, and generates the control signals SI and SQ for the pair of sign inverters 1001I and 1001Q and the control signals DAI and DAQ for the pair of variable gain amplifiers 1002I and 1002Q. The control circuit 1004 includes a digital signal processing circuit (DSP) 1005 which calculates cos and sin (or refers to a memory) to generate the control signals, an encoder 1006 which converts the signal generated by the DSP 1005 into the specific control signals SI, SQ, DAI, and DAQ, and a plurality of digital/analog converters (DACs) 1007I and 1007Q which convert the digital data DAI and DAQ into analog signals to control the variable gain amplifiers 1002I and 1002Q.
Note that the same function as that of the combination of the sign inverters 1001I and 1001Q and the variable gain amplifiers 1002I and 1002Q can be implemented by four-quadrant multipliers (for example, Gilbert cells) (Japanese Patent Laid-Open No. 2004-32446 and Japanese Patent No. 3063093). FIG. 42 shows the arrangement of a vector sum phase shifter in this case. The vector sum phase shifter in FIG. 42 includes a 90° phase shifter 2000, two four-quadrant multipliers 2001I and 2001Q, combiner 2002, and control circuit 2003.
The operation of the 90° phase shifter 2000 is the same as that of the 90° phase shifter 1000. The in-phase signal VINI and the quadrature signal VINQ output from the 90° phase shifter 2000 are represented by the constellation diagram of FIG. 41B.
The four-quadrant multipliers 2001I and 2001Q change the signs and gains of outputs based on the signs and levels of control signals CI and CQ, and consequently change the amplitudes of the in-phase signal VINI and the quadrature signal VINQ and output them, respectively.
The combiner 2002 vector-combines the in-phase signal VXI and the quadrature signal VXQ output from the pair of four-quadrant multipliers 2001I and 2001Q, and outputs the combined signal to the outside as the phase shifter output VOUT. The phase shifter output VOUT is represented by the constellation diagram of FIG. 41D.
The control circuit 2003 receives the digital signal DGTL containing the information of the phase φ to be output, and generates the control signals CI and CQ for the pair of four-quadrant multipliers 2001I and 2001Q. The control circuit 2003 includes a DSP 2004, encoder 2005, and DACs 2006I and 2006Q. In the arrangement shown in FIG. 42, it is necessary to use DACs of differential analog output type as the DACs 2006I and 2006Q in the control circuit 2003.